High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory. In recent years, there has been an effort to further increase the speed of memory access.
For example, an input buffer may include resister loads coupled to positive power supply nodes and a pair of field-effect transistors having a low threshold voltage for receiving an input signal. The on-die termination provided by the resistor loads may be used for impedance matching with data lines. According to a simulation test of the input buffer, the input buffer shows ability to increase a data rate to 4.5 Gbps. Thus, the input buffer is likely to be suitable in a double data rate fourth generation synchronous dynamic random-access memory (DDR4-SDRAM) with a data rate of 3.2 Gbps.
The input buffer is also evaluated by applying a rank margining test. In a rank margining test, a reference voltage (VREF) level may be varied from a mid-point between a voltage of input high (VIH) and a voltage of input low (VIL) to test a margin of RMT as performance tolerance. The input buffer is required to operate without any errors even if the reference voltage shifts, as long as the reference voltage is in a predetermined range.
However, with the approach described above, when the VREF is shifted to a higher voltage, the time an input signal is greater than the VREF becomes shorter. The voltage level of a high pulse of the input signal becomes lower when a width of the high pulse becomes shorter. As a result, a slew rate of the input signal may deteriorate. These results suggest that the input buffer merely including the resister loads coupled to the positive power supply nodes, and the pair of field-effect transistors having the low threshold voltage may not be acceptable in the DDR4-SDRAM. Thus, an input buffer which has a high data rate sufficient for a data rate of DDR4-SDRAM and performance tolerance against a shift of a reference voltage may be desired.